1. Technical Field
The embodiments relate to a semiconductor device including plural semiconductor elements and a manufacturing method thereof.
2. Description of the related art
As electronic equipment has increased in functionality and decreased in size, semiconductor devices such as the semiconductor integrated circuit device installed in such electronic equipment are also desired to have higher functionality, higher operating speed, and further, smaller size and lighter weight.
Therefore, with the semiconductor device, plural semiconductor elements are mounted so as to be layered on a supporting base (supporting board) such as a circuit board.
Thus, a configuration having plural semiconductor elements may occur to make semiconductor device having desired function by combining a logic function element such as a microprocessor and a semiconductor storage element such as non-volatile memory.
In such a case, the circuit function and circuit size of the logic function element and semiconductor storage element are completely different, whereby the external dimensions thereof generally differ.
Also, the semiconductor elements normally have a rectangular planar shape.
Accordingly, in a layered state, there may be cases wherein at least one edge of a semiconductor element positioned on the upper side extends (protrudes) in wing form to the outer side of a semiconductor element positioned on the lower side (supporting base side).
The connection with the supporting base is used for connecting the supporting base to electrode terminals of the semiconductor elements, and connecting the supporting base to the electronic equipment. There may be a case wherein a disposal configuration of connection with the supporting base cause the leading direction and/or leading locations of the bonding wire led from the plural semiconductor elements to be restricted.
In such a case, the layered semiconductor elements are layered in a direction whereby the center lines thereof intersect in different directions (rotationally disposed), and freedom of the lead such as the bonding wire from the electrode terminals of the semiconductor elements can be increased.
At this time, there may be cases wherein both edges or at least one edge of the semiconductor elements placed on the upper side, extend (protrude) in wing form in a different direction from the electrode terminal placing unit (placing edge) of the semiconductor element placed on the lower side (supporting base side).
Note that modes of mounting the semiconductor element onto the supporting base may include a mode for mounting on the supporting base with a so-called flip-chip (face-down) mode, or a mode for mounting on the supporting base in a face-up state whereby the electrode terminal pads are connected to the electrode terminals on the supporting base with a wire bonding method.
These mounting modes are appropriately selected and combined to mount the plural semiconductor elements in a layered manner on the supporting base, but as described above, a state wherein a portion of the semiconductor element positioned on the upper side is extended (protruded) in wing form on the outer side of the semiconductor element positioned on the lower side (supporting base side) so as to extend past the edge portion of the semiconductor element positioned on the lower side may occur depending on the dimensional relation between the mutual semiconductor elements and/or the direction of mounting.
Further, in the event of placing plural semiconductor elements in a layered manner, there may be cases wherein a so-called spacer (gap holding member) is placed between the mutual semiconductor elements, and a space is provided between the semiconductor elements.
At this time, there may be cases wherein at least one edge of the semiconductor element positioned on the upper side extends (protrudes) in wing form past the spacer which is the supporting base.
Also, with the semiconductor device, even if a layered configuration of semiconductor elements is included as describe above, reducing the thickness (height) thereof is demanded.
On the other hand, various demands continue to be made regarding the combination of layered semiconductor elements as well.
Therefore, reducing the thickness of the semiconductor elements is also necessary.
In the case that semiconductor elements thus having the thickness thereof reduced are employed in the event of configuring the layered configuration and the semiconductor elements are positioned on the upper side, as described above, the electrode terminal units on the semiconductor elements positioned on the upper side can result in being positioned in such an extended portion.
In such a case, if wire bonding is attempted to the electrode terminal of the semiconductor element positioned on the upper side, the extended portion of the semiconductor element warps (bends toward the bottom side, supporting base side), and since sufficient pressure is not applied, normal wire bonding is not performed.
Also, if a greater pressure is applied, there may be cases wherein the extended portion of the semiconductor elements positioned on the upper side is damaged.
Thus, with a semiconductor element employing a configuration of layering semiconductor elements, in the event of performing wire bonding of the semiconductor element positioned on the upper side to the electrode terminal, in order to prevent deformity of the extended portion of the semiconductor elements, various proposals have been made.
A configuration has been proposed wherein a first semiconductor chip, and a second semiconductor chip which is larger than the first semiconductor chip and which is disposed in a layered manner on the first semiconductor chip, are disposed on a board, and a mount member is placed between the second semiconductor chip and the board (e.g. see Japanese Laid-open Patent Publication No. 2001-320014).
Also, a configuration has been proposed wherein a first semiconductor chip, and a second semiconductor chip which is larger than the first semiconductor chip and which is disposed in a layered manner on the first semiconductor chip, are disposed on a board, and plural column-shaped supporting units are placed between the second semiconductor chip and the board (e.g. see Japanese Laid-open Patent Publication No. 2005-197491).